Catalog Entry (2012-2013):

3130 Switching Circuit Theory(4) Combinational circuit analysis and design. State machine analysis and design. Includes synchronous/clock mode circuits and asynchronous sequential circuits. Minimization, race and hazard elimination are covered. Circuits are implemented in discrete logic and in CPLD and FPGA devices. VHDL hardware description language is used to describe circuits. Circuits are implemented in discrete logic and in CPLD/FPGA devices. Prereq: CEEN 1060.


Fundamentals of Digital Logic with VHDL Design: Brown

Class/Laboratory Schedule:

The lecture portion of the course will meet for three university hours each week. The laboratory portion will meet for three university hours each week.

Course Outcomes:

The student who successfully completes this course will be able to:

  1. Minimize Boolean expressions using Boolean algebra, Karnaugh maps and formalized methods such as Quine-McClusky.(9b)
  2. Analyze state machines by using next-state equations and state diagrams.(9b)
  3. Design a state machine that meets specified operational requirements (9b)
  4. Minimize state machines.(9bf)
  5. Design combinational circuits using VHDL.(4,9if)
  6. Implement combinational circuits using both standard integrated circuits and programmable logic integrated circuits.(4,9def)
  7. Design state machines using VHDL.(4,9if)
  8. Implement state machines using both standard integrated circuits programmable logic integrated circuits.(4,9def)
  9. Write formal reports on the results of laboratory exercises. (13)

Course Topics:

  1. Combinational Circuits
    1. Boolean Algebra Reduction
    2. Karnaugh Maps
    3. Formal Minimization Techniques
    4. Implementation Techniques
    5. MSI Circuitry
    6. Hardware Description Languages (VHDL)
  2. State Machines
    1. Synchronous/Clock Mode Circuits
    2. Minimization of Incompletely Specified State Tables
    3. Asynchronous Sequential Circuits
  3. Programmable Logic Devices
    1. Programmable Read Only Memory (PROM)
    2. Programmable Logic Array (PLA)
    3. Programmable Array Logic (PAL)
    4. Generic Array Logic (GAL)
    5. Combinational Logic Functions From PALs.
    6. Clocked State Machine Design Using PALs
    7. Asynchronous State Machine Design Using PALs
    8. Analysis of Fuse Maps

The Reason this Course is in the Program:

This course refreshes and expands on the students' knowledge on basic logic circuits which were taught in the freshman Computer and Electronics Engineering Fundamentals course. One of its primary purposes is to teach the design and implementation of state machines using traditional integrated circuits. A second purpose is to introduce modern design techniques, specifically the use of VHDL in designing combinational and sequential circuits and implementing the designs in PAL, CPLD and FPGA integrated circuits.

Prepared by:

Roger D. Sash - January 18, 2001